SAT-Based Data-Flow Mapping Onto Array Processor

Yukio Miyasaka, Masahiro Fujita

Abstract: Recently, it has been common to perform parallel processing in machine learning. Reconfigurable array processor is drawing attention in terms of easy custom adjustment and high performance. We propose a method to map a data-flow onto an array processor using a SAT solver. The proposed method is combined with an automatic transformation method, which changes the order of calculations, to generate a more efficient computation scheme. We have solved mapping problems of matrix-vector multiplication. In our experiment, a SAT solver was more scalable than an ILP solver. Our method handled a dataflow of more than a hundred nodes using MAC operation. The automatic transformation under the associative and commutative laws is less scalable but successfully reduced calculation time. We have also mapped sparse matrix multiplication with varying latency and throughput and generated faster schedules utilizing the sparsity.