A 64b/66b Line Encoding for High Speed Serializers

jatindeep singh

Abstract:

With advancement in technology, there is an increase
in the size of current files, thus leading to a demand in increase
in data transfer rate. Line encoding can potentially help in
increasing speeds by dramatically reducing overheads without
necessitating improvements in SERDES devices. Conventionally
this technique is suited for optical fiber communication which
involves very low BER, but can also be extended for higher BER
by including proper error correction codes. This paper discusses
a modification in the physical layer hence increasing the transfer
rate without affecting the current communication devices. We
have implemented line encoding technique for the design of high
speed SERDES devices. The proposed 64b/66b line encoding
technique reduces additional overhead by 16% with respect to
conventional 8b/10b. Hence this technique is advantageous for
high speed communication. However, it may lead to high BER.
We have optimally selected polynomial for scrambling and
descrambling process. The proposed polynomial results in
improved efficiency of the scrambler. Algorithms have been
developed to find primitive polynomial of three non-zero
elements. Various polynomials have been generated and tested
in MATLAB. The generated polynomials have been
implemented on VHDL and hardware verification has been
successfully completed and demonstrated on Actel ProASIC 3C.
Keywords— Serializer-Deserializer (SERDES), Line Encoding
Technique, Bit Error Rate (BER), Camera Electronics, Inter
Symbol Interference (ISI), Scrambling, Descrambling, Cyclic
Redundancy Check (CRC), Parallel Data Transmission,
High Speed Serializers, Linear Feedback Shift Registers (LFSR).