BOHA: A High Performance VSLAM Backend Optimization Hardware Accelerator Using Recursive Fine-Grain H-Matrix Decomposition and Early-Computing With Approximate Linear Solver

Ye Liu, Kun Huang, Neng Zhao, Jingyuan Li, Shuang Hao, Zili Huang, Xiuyuan Qi, Xinghao Wang, Liang Zhou, Liang Chang, Jun Zhou

Abstract: Visual simultaneous localization and mapping (VSLAM) technology has been used in many intelligent applications such autonomous car, unmanned aerial vehicle (UAV) and augmented reality (AR) for localization and trajectory generation. The VSLAM usually contains the frontend computation and the backend optimization. The backend optimization is an essential part of VSLAM which helps improve the precision and dominates the computation time (~80%) of VSLAM. However, it includes large inner data dependency which is difficult to be accelerated using GPU. To address this issue, in this brief, we propose a high performance VSLAM backend optimization hardware accelerator (named BOHA). Diverse design techniques have been proposed to reduce computation latency by avoiding the data redundancy in the backend optimization, including 1) a recursive fine-grain H-matrix decomposition computing architecture to improve the hardware utilization and reduce the data movement. 2) an early-computing technique with approximate linear solver to reduce the computation latency while maintaining high precision. 3) a two-stage deep Schur elimination technique to reduce the computation latency. The proposed design has been implemented and evaluated on a Xilinx FPGA ZCU104 and achieves low computation latency (5.1 ms) with low trajectory error (0.27%), outperforming the state-of-the-art designs.