Hybrid EA-DRL Optimisation Framework for Fast-Settling Multi-Stage PLL with Adaptive Locking Control

Aowen Yang, Qin Zhang

Keywords: EA, DRL, ADPLL

TL;DR: This paper introduces a hybrid evolutionary–reinforcement learning framework that optimises multi-stage ADPLL parameters to achieve faster locking, lower jitter, and stronger robustness under dynamic and PVT variations.

Abstract: This paper presents a hybrid evolutionary algorithm and deep reinforcement learning (EA–DRL) optimisation framework for fast-settling multi-stage all-digital phase-locked loops (ADPLL). To address the coupled trade-offs among lock time, phase noise, overshoot, and robustness, a structure-aware NSGA-III algorithm (SA-NSGA-III) is developed to generate high-quality Pareto optimal static parameters that preserve the physical consistency of the two-stage ADPLL dynamics. Based on this optimised baseline, a DRL controller based on twin delayed deep deterministic policy gradient (TD3) is used to fine-tune the loop gain in real time to enhance transient convergence and steady-state accuracy. Experimental results demonstrate that the proposed framework achieves significant improvements in settling speed, jitter performance, and robustness to process, supply voltage, and temperature (PVT) variation compared to conventional static designs, reducing lock time by up to 98\% during frequency transitions and substantially improving dynamic response performance.

Submission Number: 68