ParetoRouter: VLSI Global Routing with Multi-Objective Optimization

ICLR 2026 Conference Submission8739 Authors

Keywords: Global Routing; VLSI; Multi Objective Optimization; Diffusion Model

Abstract: Global routing (GR) has been a central task in modern chip design. Many efforts, either ML-based or heuristic, have been proposed, which seek to optimize certain business goals e.g. overflow (OF) and wirelength (WL) of generated routes. Notably the recent end-to-end neural routers have shown extreme speed advantages in optimizing wirelength yet they struggle in efficiency to reduce overflow. In fact, a good trade-off between the above two metrics has not been achieved, especially the overall efficiency is pursued, as often only a single metric is optimized in existing ML-based methods. To bridge this gap for more practical industry applications, we propose a flow matching-based router for GR called ParetoRouter, to achieve trade-offs between WL and OF and generate highly connected routes in high speed and quality. In the training phase, two differential metric-oriented routing results are utilized to build the training datasets and are leveraged to design an `Average Flow' between initial pins and final routings. A Pareto sampling method based on the Das-Dennis method is also devised to realize trade-offs between OF and WL in the inference phase. Extensive experimental results show that it achieves SOTA performance on the \textbf{overflow reduction} with \textbf{less superfluous routes} across all benchmarks with \textbf{x5} times speedup over the peer SOTA ML-based method.

Primary Area: applications to computer vision, audio, language, and other modalities

Submission Number: 8739