Towards Improving Verification Productivity with Circuit-Aware Translation of Natural Language to SystemVerilog Assertions

Chuyue Sun, Christopher Hahn, Caroline Trippel

Abstract:

Assertion-based verification is a technique to ensure that a circuit design conforms to its specification and help detect errors early in the design process.
It is enabled by powerful industry and open-source model-checking tools that automatically prove or disprove an assertion for a given circuit design.
Formalizing a circuits requirement, however, involves a significant manual effort by verification engineers to translate requirements in natural language into a formal assertion language.
In this extended abstract, we introduce a framework that utilizes Large Language Models (LLMs) pre-trained on natural language and code to improve verification productivity by automating the formalization process.
In particular, we report on the current progress of developing \texttt{nl2sva}, a framework for circuit-aware translations of natural language to the most frequently used assertion language, SystemVerilog Assertions (SVA).