Bayesian Network Structure Learning using Digital Annealer

Shikuri Yuta

Keywords: Bayesian Network Structure Learning, Digital Annealer

TL;DR: Bayesian Network Structure Learning using Digital Annealer

Abstract: Annealing processors, which efficiently solve a quadratic unconstrained binary optimization (QUBO), are a potential breakthrough in improving the accuracy of score-based Bayesian network structure learning. However, currently, the bit capacity of an annealing processor is very limited. To utilize the power of annealing processors, it is necessary to encode score-based learning problems into QUBO within the upper bound of bits. In this paper, we propose a novel approach with direct encoding of candidate parent sets in the form of Cartesian products. Experimental results on benchmark networks with $27$ to $70$ variables show that our approach requires lesser bits than the bit capacity of the second-generation Fujitsu digital annealer, a fully coupled annealing processor developed by with semiconductor technology. Moreover, we demonstrate that the digital annealer with our conversion method consistently outperforms the state-of-the-art heuristic algorithms on the benchmark networks.

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