EfficientRefiner: An Efficient Refinement Method over Black-Box Optimization in Macro Placement

ji deng, Jun Gao, Zhao Li, Ji Zhang

Keywords: Chip Placement, Refinement, Gradient Descent

Abstract:

A refinement stage on macro placements generated by SOTA off-the-shelf placers can further improve the layout quality, as this stage compensates for the sub-optimality arising from lack of full-layout awareness in RL-based placers, as well as the quality degradation resulting from the overlap-resolving legalization step in analytical placers.
Nevertheless, existing RL-based refinement techniques often incur high computational cost. This paper proposes EfficientRefiner, which leverages an efficient analytical framework to refine macro layouts produced by existing placement approaches, achieving reduced computational overhead while improving layout quality.
EfficientRefiner encodes macro positions as learnable vectors and optimizes an objective function that integrates both target metrics and placement constraints via gradient descent.
It introduces a novel fine-grained pairwise overlap formulation tailored for macro refinement, which overcomes the limitations of prior density-based objectives in analytical methods by effectively minimizing overlaps without inducing excessive spreading that could degrade layout quality. Moreover, EfficientRefiner enhances efficiency and scalability through pruning algorithms and GPU acceleration.
Experimental results show that, when considering both HPWL and regularity metrics for optimization, it improves average HPWL by **7.20%–34.71%** within 10 minutes on the ISPD2005 benchmark, and achieves average timing gains of **20\% WNS and 29% TNS** on PPA-supported ChiPBench circuits.

Primary Area: applications to physical sciences (physics, chemistry, biology, etc.)

Submission Number: 18185