EfficientRefiner: An Efficient Refinement Method over Black-Box Optimization in Macro Placement

ICLR 2026 Conference Submission18185 Authors

Keywords: Chip Placement, Refinement, Gradient Descent

Abstract: A refinement stage on macro placements generated by state-of-the-art methods can further improve the layout quality, as this stage compensates for the sub-optimality arising from lack of full-layout awareness in RL-based methods, as well as the quality degradation resulted from the overlap-resolving legalization step in analytical approaches. However, existing RL-based refinement techniques often incur high computational cost. To reduce the computation overhead introduced by the additional refinement stage, this paper proposes EfficientRefiner, which leverages the efficiency of analytical framework to refine placement from any BBO placement approaches. EfficientRefiner encodes macro positions as learnable vectors and optimizes an objective function that integrates both target metrics and placement constraints via gradient descent. It introduces a novel fine-grained pairwise overlap formulation tailored for macro refinement, which overcomes the limitations of prior density-based objectives in analytical methods by effectively minimizing overlaps without inducing excessive spreading that could degrade layout quality. Moreover, EfficientRefiner enhances efficiency and scalability through pruning algorithms and GPU acceleration. Experimental results show that, when considering both HPWL and regularity metrics for optimization, it improves average HPWL by **7.20%–34.71%** within 10 minutes on the ISPD2005 benchmark, and achieves **20% WNS and 29% TNS** gains on PPA-supported ChiPBench circuits.

Primary Area: applications to physical sciences (physics, chemistry, biology, etc.)

Submission Number: 18185