LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation
Keywords: Large Language Models, Automated Chip Design, Design Verification
TL;DR: We present LLM4DV, an open-source framework to explore the potential of large language models (LLMs) for hardware verification. Evaluating five models across eight designs, our analysis shows that LLMs can lead to efficient test stimuli generation.
Abstract: Hardware design verification (DV) is a process that checks the functional equivalence of a hardware design against its specifications, improving hardware reliability and robustness. A key task in the DV process is the test stimuli generation, which creates a set of conditions or inputs for testing. A major challenge is that existing approaches to test stimuli generation require human effort due to the complexity and specificity of the test conditions required for an arbitrary hardware design. We seek an efficient and automated solution that takes advantage of large language models (LLMs). LLMs have shown promising results for improving hardware design automation, but remain under-explored for hardware DV. In this paper, we propose an open-source benchmarking framework called LLM4DV that efficiently orchestrates LLMs for automated hardware test stimuli generation. Our analysis evaluates five LLMs using six prompting improvements over eight hardware designs and provides insight for future work on LLMs for efficient DV.
Primary Area: datasets and benchmarks
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Submission Number: 8593
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