OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generation

ICLR 2026 Conference Submission16960 Authors

Keywords: electronic design automation, analog circuits, reinforcement learning, layout design, parasitic-aware, dataset generator

TL;DR: Osiris is a scalable pipeline for generating analog IC datasets comprising circuit variations and performance metrics enabling ML-driven research in electronic design automation.

Abstract: The automation of analog integrated circuit (IC) design remains a longstanding challenge, primarily due to the intricate interdependencies among physical layout, parasitic effects, and circuit-level performance. These interactions impose complex constraints that are difficult to accurately capture and optimize using conventional design methodologies. Although recent advances in machine learning (ML) have shown promise in automating specific stages of the analog design flow, the development of holistic, end-to-end frameworks that integrate these stages and iteratively refine layouts using post-layout, parasitic-aware performance feedback is still in its early stages. Furthermore, progress in this direction is hindered by the limited availability of open, high-quality datasets tailored to the analog domain, restricting both the benchmarking and the generalizability of ML-based techniques. To address these limitations, we present Osiris, a scalable dataset generation pipeline for analog IC design. Osiris systematically explores the design space of analog circuits while producing comprehensive performance metrics and metadata, thereby enabling ML-driven research in electronic design automation (EDA). In addition, we release a dataset consisting of 64,200 circuit variations generated with Osiris, accompanied by a reinforcement learning (RL)–based baseline method that exploits Osiris for analog design optimization.

Primary Area: datasets and benchmarks

Submission Number: 16960