Analog Circuit Topology Design and Sizing with Flow Matching Graph Learning

ICLR 2026 Conference Submission17818 Authors

Keywords: analog circuit design automation, topology generation, flow matching on graphs, graph transformers

TL;DR: We present a flow matching graph model for end-to-end analog circuit topology design and device sizing, achieving SOTA performances on standard benchmarks.

Abstract:

The soaring demand for electronic devices calls for novel and more efficient analog circuits design.
Deep generative models have shown promise in assisting topology, parameter sizing, and layout design process, but existing approaches treat these tasks separately and lack generalizability across diverse problem settings.
In this work we introduce a flow matching model for automatic analog circuit design, which achieves high-quality sampling across a variety of topologies and representations.
Our model showcases state-of-the-art performances on end-to-end topology design and sizing on the Open Circuit Benchmark (OCB) dataset, and on transistor-level topology generation on the AnalogGenie dataset.
Code and models are provided as external supplementary files to this submission.

Primary Area: applications to physical sciences (physics, chemistry, biology, etc.)

Submission Number: 17818