IC-DLC: Differentiable Logic Circuits for Hardware-Friendly Image Compression

Till Aczel, David F. Jenny, Simon Jonas Bührer, Andreas Plesner, Antonio Di Maio, Roger Wattenhofer

Keywords: learned image copmression, differentiable logic circuits

Abstract: Neural image codecs achieve higher compression ratios than traditional hand-crafted methods such as PNG or JPEG-XL, but often incur substantial computational overhead, limiting their deployment on energy-constrained devices such as smartphones, cameras, and drones. We propose Image Compression with Differentiable Logic Circuits (IC-DLC), a hardware-aware codec where we train lookup tables to combine the flexibility of neural networks with the efficiency of Boolean operations. Experiments on grayscale benchmark datasets show that IC-DLC outperforms traditional codecs in compression efficiency while allowing substantial reductions in energy consumption and latency. These results demonstrate that learned compression can be hardware-friendly, offering a promising direction for low-power image compression on edge devices.

Submission Number: 18