GRIT: Graph-Biased Transformers for Hardware-Aware Quantum Layout via Reinforcement Learning Search

ICLR 2026 Conference Submission19496 Authors

Keywords: Quantum compilation, qubit layout, graph transformer, reinforcement learning, hardware-aware cost

TL;DR: A graph-biased Transformer with policy-guided MCTS learns hardware-aware qubit layouts that reduce makespan versus strong transpiler baselines under matched budgets.

Abstract: Quantum computing holds transformative potential, yet today’s hardware remains small, noisy, and connectivity-limited, making efficient compilation a critical challenge. Existing compilers operate on hardware coupling graphs and introduce SWAP operations to satisfy restricted qubit interactions, which often increases circuit depth, execution time, and error rates. Reinforcement learning (RL) has recently been explored for mapping and routing, but prior approaches still lead to long execution times and degraded fidelity on real devices, limiting practical effectiveness. We propose a hardware-aware compilation framework that integrates representation learning with search. Specifically, we design a graph-biased Transformer that jointly encodes logical and physical qubit graphs with structural biases, and train policies via group-relative policy optimization using a blocking-aware simulator aligned with true execution-time objectives. During inference, the learned policy is combined with Monte Carlo tree search to refine mappings under limited simulation budgets. Experiments demonstrate that this integrated learning-and-search framework achieves scalable, hardware-aware compilation with improved fidelity and efficiency across diverse circuits and architectures.

Primary Area: applications to physical sciences (physics, chemistry, biology, etc.)

Submission Number: 19496