EuclidNets: Combining hardware and architecture design for Efficient Inference and Training

Mariana Oliveira Prazeres, Xinlin Li, Vahid Partovi Nia, Adam M Oberman

Keywords: deep Neural Networks, hardware aware architecture, compressed models

TL;DR: A compressed network designed to be implemented on low precision custom chips which doubles efficiency (as measured by logic gates) with insignificant loss of accuracy.

Abstract: In order to deploy deep neural networks on edge devices, compressed (resource efficient) networks need to be developed. While established compression methods, such as quantization, pruning, and architecture search are designed for conventional hardware, further gains are possible if compressed architectures are coupled with novel hardware designs. In this work, we propose EuclidNet, a compressed network designed to be implemented on hardware which replaces multiplication, $wx$, with squared difference $(x-w)^2$. EuclidNet allows for a low precision hardware implementation which is about twice as efficient (in term of logic gate counts) as the comparable conventional hardware, with acceptably small loss of accuracy. Moveover, the network can be trained and quantized using standard methods, without requiring additional training time. Codes and pre-trained models are available at \url{http://github.com/anonymous/}.

Code Of Conduct: I certify that all co-authors of this work have read and commit to adhering to the NeurIPS Statement on Ethics, Fairness, Inclusivity, and Code of Conduct.