Explainable Error Detection in Integrated Circuits Image Segmentation via Graph Neural Networks

ICLR 2026 Conference Submission14756 Authors

Keywords: IC image segmentation, segmentation error detection, graph neural networks

TL;DR: The paper proposes a error detection method of IC image segmentation using graph neural networks.

Abstract: The nanoscale complexity of modern integrated circuits (ICs) and the low error tolerance in segmentation tasks pose significant challenges for automated quality control. While deep learning–based IC segmentation has advanced, most approaches still rely on manual inspection due to limited error interpretability. Existing CNN-based error detectors operate holistically on entire images, making it difficult to localize specific faults such as open or short circuits. We propose a novel, explainable error detection framework based on Graph Neural Networks (GNNs). By converting each connected component of a segmentation mask into a feature-annotated graph, our method enables localized reasoning and identification of segmentation errors through graph classification. This formulation allows the model to detect outlier components and precisely highlight erroneous regions, offering strong interpretability. Experiments across diverse IC layouts and imaging conditions demonstrate the robustness and generalizability of our approach, enabling accurate and interpretable error detection at the component level.

Primary Area: applications to computer vision, audio, language, and other modalities

Submission Number: 14756