Explainable Error Detection in Integrated Circuits Image Segmentation via Graph Neural Networks

TMLR Paper6809 Authors

Abstract: Automated IC image segmentation for hardware assurance remains challenging due to nanoscale complexity, low error tolerance, and the limited interpretability of current deep-learning–based segmentation methods. Existing CNN-based error detectors analyze whole images, making it difficult to localize specific faults. We introduce an explainable GNN-based framework that converts each connected component of a segmentation mask into a feature-annotated graph, enabling localized reasoning and component-level error classification. This graph formulation allows the model to detect outlier components and precisely highlight erroneous regions. Experiments across diverse IC layouts and imaging conditions show that the method is robust, generalizable, and provides accurate, interpretable error detection.

Submission Type: Regular submission (no more than 12 pages of main content)

Assigned Action Editor: ~C.V._Jawahar1

Submission Number: 6809