Error elimination ECC by horizontal error detection and vertical-LDPC ECC to increase data-retention time by 230% and acceptable bit-error rate by 90% for 3D-NAND flash SSDs

Shun Suzuki, Yoshiaki Deguchi, Toshiki Nakamura, Kyoji Mizoguchi, Ken Takeuchi

Abstract: Cross Error Elimination (XEE) ECC with Horizontal Error Detection (HED) and Vertical-LDPC (V-LDPC) is proposed to extend the data-retention lifetime of 3D-TLC NAND flash-based SSD. HED improves the error correction capability of LDPC ECC by evaluating the error bits in the horizontal direction which means the column direction. Moreover, V-LDPC improves the worst reliability in each WL in the vertical row direction through three (Upper/Middle/Lower) pages. This paper investigates the reliability improvement of 3D-TLC NAND flash memory by XEE ECC. As a result, the data-retention lifetime and the acceptable bit-error rate (BER) are extended by 230% and 90%, respectively.