Toshiki Nakamura

Researcher, AVS Software, Sony Advanced Visual Sensing

Joined

May 2023

Names

Toshiki Nakamura (Preferred)

Emails

****@sony.com (Confirmed)

Personal Links

DBLP

ORCID

Career & Education History

Researcher

AVS Software, Sony Advanced Visual Sensing (sony.com)

2024 – Present

Researcher

Research Division 3, Sony Semiconductor Solutions Corporation (sony.com)

2022 – 2024

Researcher

R&D Center, Sony Group Corporation (sony.com)

2019 – 2022

Advisors, Relations & Conflicts

Coworker

Dimche Kostadinov

2024 – Present

Coworker

Eshar Ben Dor

2024 – Present

Expertise

sparse inference

token reduction

image classification

2024 – 2026

network compression

pruning

quantization

2019 – 2024

Publications

n-hot: Efficient Bit-Level Sparsity for Powers-of-Two Neural Network Quantization
Yuiko Sakuma, Hiroshi Sumihiro, Jun Nishikawa, Toshiki Nakamura, Ryoji Ikegaya
- 16 May 2023
- OpenReview Archive Direct Upload
- Readers: Everyone
n-hot: Efficient bit-level sparsity for powers-of-two neural network quantization
Yuiko Sakuma, Hiroshi Sumihiro, Jun Nishikawa, Toshiki Nakamura, Ryoji Ikegaya
- Published: 01 Jan 2021, Last Modified: 16 May 2023
- CoRR 2021
- Readers: Everyone
Privacy-Aware Data-Lifetime Control NAND Flash System for Right to be Forgotten with In-3D Vertical Cell Processing
Shun Suzuki, Kyoji Mizoguchi, Hikaru Watanabe, Toshiki Nakamura, Yoshiaki Deguchi, Keita Mizushina, Ken Takeuchi
- Published: 01 Jan 2019, Last Modified: 16 May 2023
- A-SSCC 2019
- Readers: Everyone
Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories
Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi
- Published: 01 Jan 2019, Last Modified: 16 May 2023
- IEEE J. Solid State Circuits 2019
- Readers: Everyone
3-D NAND Flash Value-Aware SSD: Error-Tolerant SSD Without ECCs for Image Recognition
Yoshiaki Deguchi, Toshiki Nakamura, Atsuna Hayakawa, Ken Takeuchi
- Published: 01 Jan 2019, Last Modified: 16 May 2023
- IEEE J. Solid State Circuits 2019
- Readers: Everyone
Layer-by-layer Adaptively Optimized ECC of NAND flash-based SSD Storing Convolutional Neural Network Weight for Scene Recognition
Keita Mizushina, Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi
- Published: 01 Jan 2018, Last Modified: 16 May 2023
- ISCAS 2018
- Readers: Everyone
Endurance-based Dynamic VTHDistribution Shaping of 3D-TLC NAND Flash Memories to Suppress Both Lateral Charge Migration and Vertical Charge De-trap and Increase Data-retention Time by 2.7x
Shun Suzuki, Yoshiaki Deguchi, Toshiki Nakamura, Ken Takeuchi
- Published: 01 Jan 2018, Last Modified: 16 May 2023
- ESSDERC 2018
- Readers: Everyone
9.1x Error acceptable adaptive artificial neural network coupled LDPC ECC for charge-trap and floating-gate 3D-NAND flash memories
Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi
- Published: 01 Jan 2018, Last Modified: 16 May 2023
- CICC 2018
- Readers: Everyone
Data-Aware Partial ECC with Data Modulation of ReRAM with Non-volatile In-memory Computing for Image Recognition with Deep Neural Network
Atsuna Hayakawa, Toshiki Nakamura, Yoshiaki Deguchi, Kazuki Maeda, Ken Takeuchi
- Published: 01 Jan 2018, Last Modified: 16 May 2023
- ISCAS 2018
- Readers: Everyone
Error elimination ECC by horizontal error detection and vertical-LDPC ECC to increase data-retention time by 230% and acceptable bit-error rate by 90% for 3D-NAND flash SSDs
Shun Suzuki, Yoshiaki Deguchi, Toshiki Nakamura, Kyoji Mizoguchi, Ken Takeuchi
- Published: 01 Jan 2018, Last Modified: 16 May 2023
- IRPS 2018
- Readers: Everyone

View all 11 publications

Toshiki Nakamura

Names

Emails

Personal Links

Career & Education History

Advisors, Relations & Conflicts

Expertise

Publications

Co-Authors