Yi Liu

Full Professor, Xi'an University

Joined

January 2023

Names

Yi Liu (Preferred)

Emails

****@mail.xidian.edu.cn (Confirmed)

Personal Links

Career & Education History

Full Professor

Xi'an University (xidian.edu.cn)

Present

Advisors, Relations & Conflicts

Coauthor

Present

Coauthor

2019 – Present

Expertise

VLSI

Present

Publications

Ultra-low Latency Adaptive Local Binary Spiking Neural Network with Accuracy Loss Estimator
Changqing Xu, Yijian Pei, Zili Wu, Yi Liu, Yintang Yang
- Published: 01 Jan 2022, Last Modified: 12 May 2023
- CoRR 2022
- Readers: Everyone
Comparison in radiation tolerance between FLR planar junction termination and positive bevel edge termination for power diodes
Xinfang Liao, Yi Liu, Changqing Xu, Chen Wang, Yintang Yang
- Published: 01 Jan 2022, Last Modified: 12 May 2023
- Microelectron. J. 2022
- Readers: Everyone
Ultra-low Latency Spiking Neural Networks with Spatio-Temporal Compression and Synaptic Convolutional Block
Changqing Xu, Yi Liu, Yintang Yang
- Published: 01 Jan 2022, Last Modified: 12 May 2023
- CoRR 2022
- Readers: Everyone
A Q-Learning-Based Fault-Tolerant and Congestion-Aware Adaptive Routing Algorithm for Networks-on-Chip
Yi Liu, Rujia Guo, Changqing Xu, Weng Xiaodong, Yintang Yang
- Published: 01 Jan 2022, Last Modified: 12 May 2023
- IEEE Embed. Syst. Lett. 2022
- Readers: Everyone
Machine Learning Regression based Single Event Transient Modeling Method for Circuit-Level Simulation
Changqing Xu, Yi Liu, Xinfang Liao, Jialiang Cheng, Yintang Yang
- Published: 01 Jan 2021, Last Modified: 12 May 2023
- CoRR 2021
- Readers: Everyone
Direct Training via Backpropagation for Ultra-low Latency Spiking Neural Networks with Multi-threshold
Changqing Xu, Yi Liu, Yintang Yang
- Published: 01 Jan 2021, Last Modified: 12 May 2023
- CoRR 2021
- Readers: Everyone
SRNoC: An Ultra-Fast Configurable FPGA-Based NoC Simulator Using Switch-Router Architecture
Changqing Xu, Yi Liu, Yintang Yang
- Published: 01 Jan 2020, Last Modified: 12 May 2023
- IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
- Readers: Everyone

Co-Authors